Configurable integrated circuits (“ICs”) can be used to implement circuit functionality designed by a user (“user design”) on an IC without having to fabricate a new IC for each design. One example of a configurable IC is a field programmable gate array (“FPGA”). A configurable IC has several circuits for performing different operations. Configurable circuits can be configured by configuration data to perform a variety of different operations. These circuits can range from logic circuits (e.g., configurable look-up tables, or “LUTs”) to interconnect circuits (e.g., configurable multiplexers). The circuits of a configurable IC are often made up of a multitude of transistors, metal and/or polysilicon wires, and/or other elements (e.g., capacitors, resistors, etc.).
During the manufacture of a configurable IC it is possible for flaws to affect the operation of the IC. In addition to flaws, configurable ICs that use minimum width (or near-minimum width) transistors for a particular manufacturing technology are subject to large transistor to transistor variation. These variations can cause individual transistors to operate more slowly than required. In some cases the flaws and/or variations are manifested as malfunctioning circuit elements (e.g., stuck outputs). In other cases, the flaws and/or variations are manifested as substandard performance (e.g., excessive propagation delay). Any slow or non-functioning circuit element may potentially render the configurable IC unusable. Thus, all transistors and wires must be tested on every configurable IC to guarantee that the IC is properly functioning.
Traditional test techniques aggregate the performance of a large number of transistors and wires together into a single measurement. Thus, when some transistors and/or wires are faster than the specified performance limit while a single transistor is slower it is possible for a path that includes the slow transistor to pass the test criteria. This phenomenon is of particular concern in programmable logic because the performance path may be extremely variable (due to the wide variability in end-user designs) and is typically not the same path that is used to test the IC.
Existing IC test methods (e.g., “scan” testing that uses automatic test pattern generation or “ATPG”) measure performance by propagating a single edge through the circuit under test. In contrast, when operating in user mode, a configurable IC will have multiple operational paths and/or circuits, typically operating at a high switching rate (measured in MHz or GHz). When running at a high switching rate, the power supply to the transistors in the IC will be stressed, the temperature of the circuit will be elevated, and the on-chip decoupling capacitors will be charging and discharging. The effect of these stresses on the performance of the IC is not fully measured using traditional IC test methods.